1) Field of the Invention
The present disclosure relates to a semiconductor packaging device and a method manufacturing the same, particularly the application of a fan-out package in which no carrier is required for a die cut from a wafer according to a conductive routing layer as a substrate created by the redistribution layer technique.
2) Description of the Prior Art
In most modern semiconductor packaging techniques, the IC chip(s) should be encased in encapsulation material first and match created fan-out areas based on circuits or a built-up redistribution layer on a substrate for additions of more I/O points on extra space such as fan-out area.
As the functions of electronic products get complicated, more and more I/O connections should be applicable to IC chips in the upstream industry as well as limited layout space during corresponding semiconductor packaging and become challenges for the prevalent application like Package on Package (POP) because of more I/O points designed on limited space.
Contributing to a compact low-cost package, the technology of Fan-out Wafer Level Packaging (FoWLP), which had replaced traditional PCBs since 2016 when the components such as A10 processor and antenna switch module were mounted in iPhone7, are adopted by more and more chipmakers.
There have been multiple patents for fan-out packaging disclosed as follows:
U.S. 62/082,557 disclosed a fan-out wafer level package and a method of manufacturing the same. In one embodiment, a package comprises a first routing layer, a first die mounted on a top surface of the first routing layer, and a first molding compound in which the first die on the first routing layer is encased. A plurality of first conductive pillars is extended from a bottom surface of the first routing layer. A second die is mounted on a top surface of a second routing layer and the plurality of first conductive pillars is designed on the top surface of the second routing layer. A second molding compound is used to encase the first molding compound, the first routing layer, the plurality of first conductive pillars, and the second die on the second routing layer. In one embodiment, a plurality of conductive bumps (for example, solder balls) is extended on a bottom surface of the second routing layer.
TW I 1351088 disclosed a wafer level chip scale package, which comprises a die with a plurality of bonding pads on the die's active surface, an encapsulation body sealing the die's five surfaces, a patterned polymer layer, and a plurality of patterned metal lines covering the patterned polymer layer partially and electrically connected to a plurality of bonding pads on the die's active surface. A wafer level chip scale package features: the patterned polymer layer constitutes a fan-out sidestep structure on the die's active surface and a partial area outside the active surface; the fan-out sidestep structure is structurally elevated at a terminal point and forms holes opposite to a plurality of bonding pads on the die's active surface for exposing all bonding pads; the plurality of patterned metal lines developed on the patterned polymer layer contribute to electrical connections between a plurality bonding pads on a die's active surface and a plurality of patterned metal lines on the polymer layer of the sidestep structure; a shielding layer covers a plurality of patterned metal lines and the patterned polymer layer partially and allows a surface in which a plurality of patterned metal lines on the elevated patterned polymer layer in the sidestep structure is positioned to be exposed.
TW 104139373 disclosed fan-out POP (Package on Package) SIP (System in Package) with dummy dies and a method of manufacturing the same. In an exemplary embodiment, a package comprises a first fan-out layer, a fan-out redistribution layer (RDL) on the first fan-out layer, and a second fan-out layer on the fan-out RDL. The first fan-out layer comprises one or a plurality of first device dies and first molded plastic material extended along lateral sides of the one or plurality of first device dies. The second fan-out layer comprises one or a plurality of device dies connected to the fan-out RDL, dummy dies connected to the fan-out RDL, and second molded plastic material extended along lateral sides of the one or plurality of second device dies and the dummy dies. The fan-out RDL is used to electrically connect the one or plurality of first device dies and the one or plurality of second device dies; the dummy dies are void without any active device. As such, a package is free from warpage induced by difference in material.
TW I298193 disclosed a semiconductor packaging device which comprises: a cavity or a slot on a carrier; at least a chip comprising a back surface as well as first bonding pads with active surfaces, fixed in the cavity, and allowing the active surfaces to be exposed; a first insulating barrier designed on the carrier as well as the active surfaces and comprising first conductive clearance holes opened on the first insulating barrier and interconnecting the first bonding pads; a multi-layer structure designed on the first insulating barrier, comprising layout circuits, second conductive clearance holes and at least a second insulating barrier, and allowing ball pads to be exposed. In the multi-layer structure, the layout circuits, the second conductive clearance holes and ball pads are electrically connected to the first conductive clearance holes and the solder balls are fixed on the ball pads. As such, a semiconductor packaging device in which redistribution and fan-out processes of ordinary flip chip packages are integrated simplifies the current flip chip ball grid array process.
U.S. Pat. No. 6,770,959B2 disclosed a semiconductor package without substrate and a method of manufacturing the same wherein the method presents an interim substrate which has a front surface covered with a solder mask at selected locations. The front surface not covered by the solder mask comprises a plurality of lead layers and a plurality of die pad layers. The top side of a die pad layer adheres to a chip. The chip and lead layers are electrically connected by a plurality of bonding wires. The chip, the bonding wires, the solder mask, the lead layers and the die pad layers are covered by molded resin. With a package singularized, the interim substrate is removed in an etching process for development of a semiconductor package without substrate.
However, the fan-out wafer level packaging techniques are available to chipmakers preferably rather than the back-end packaging industry under business pressure and deserve to be promoted for probable effects with dies manufactured on wafers.